Each memory cell of Electrically programmable read only memory (EPROM) which is representative of the nonvolatile memory devices is, as shown in FIG. 1, characterized by a floating gate 4 which is separated by a layer of insulating material (commonly called tunneling oxide layer) disposed on a channel area between a source area 6 and a drain area 6 in a semiconductor substrate 1, and a control gate 7 formed on an insulating layer 5 which is interposed between both the gates 4 and 7.
A high positive voltage applied to the control gate and drain of such an electrically erasable programmable read only memory (EEPROM) cell causes hot electrons in the vicinity of the drain to be generated and these electrons have enough energy to pass over the potential energy barrier of the tunneling oxide layer and charge the floating gate.
The stored charges in the floating gate alter the threshold voltage of the cell transistor and then the cell is programmed.
Also, the read operation of the memory cell is made by applying specific voltage to each of the source and drain area and the control gate, and sensing the current which flows between the source and the drain.
Initially, EPROMs required UV light for erasing, but now it is possible to erase the contents of a ROM electrically, which is called EEPROM.
The erasing of the initially developed EEPROM cell was done by providing specific voltage to each of the source and drain area and the control gate, and thereby transporting, the charges stored in the floating gate into the drain area.
Recently, there is provided EEPROM cell having an erasure gate so as a third gate separated from the floating and control gate so as to erase the content of the cell.
In a nonvolatile memory cell as described above, the interface surface between the floating gate and the tunneling oxide layer should be not roughened so as to maintain a constant threshold voltage during the erasing.
Further it needs to improve the reliability of the device by reducing the leakage of the tunneling oxide layer due to the stress.
Generally, the floating gate is fabricated out of polysilicon and the grain size of the floating gate made of the polysilicon is around the thickness itself in a thickness of about 2000 angstroms, resulting in a severe roughness of the interface surface.
Accordingly, the floating gate having the finely formed grains has the surface of the mitigated roughness, to improve the reliability of the device.
The recently proposed EEPROM device has the tunneling oxide layer having the thickness of below 100 angstroms, the floating gate having a thickness in the range of about 2000 to 3000 angstroms and an oxide-nitride-oxide (ONO) layer adopted as an interposed insulating layer which is interposed between the floating gate and the control gate.
One of the problems in such a configured nonvolatile memory device is the roughness of the interface surface between the tunneling oxide layer and the floating gate.
The surface between the tunneling oxide layer and monocrystalline silicon layer as the substrate is not rough due to the monocrystalline silicon layer, whereas the surface between the tunneling oxide layer and floating gate is rough due to the grains of the floating gate.
FIG. 2 is an enlarged view of a portion indicated as A in FIG. 1, in which A portion is an interface portion between the floating gate and the tunneling oxide layer.
It is shown that the in case that the floating gate is fabricated out of polysilicon, the rugged interface is formed between the floating gate and tunneling oxide layer.
Such a rugged surface makes the erasure property of each cell inconsistent and the leakage of tunneling oxide layer is generated due to the stress which stems from the bi-directional erasing and programming of the cell by Fowler-Nordheim tunneling method.
Therefore, there has been proposed the methods for improving the reliability of the memory device through the improvement of the interface between the floating gate and the tunneling oxide layer.
S. Aritome discloses a technique for remarkably decreasing the leakage of the oxide layer due to the stress through the embodiment of the improved roughness of the surface which is accomplished by an ion implant with low concentration and a rapid thermal processing at low temperature, in "A reliable tunnel oxide for Flash for FLASH EEPROM", IEDM 1993.
Meanwhile, to solve the problem that it is difficult to obtain a smaller grains in case that the floating gate is made of the polysilicon, the technique is disclosed in U.S. Pat. No. 5,147,813 of which details is simply described below with reference to FIG. 3 and FIG. 4.
As shown in FIG. 3, a floating gate 4 of triple layers is formed b patterning a first, second and third layer formed over the tunneling oxide layer 3 on the substrate 1, each of which corresponds to a thin polysilicon layer 4a having a thickness of 300 to 500 angstroms, an oxide layer 4b having a thickness of 20 to 30 angstroms and a polysilicon layer 4c having a thickness of 1000 to 1500 angstroms, respectively.
FIG. 4 is an enlarged view of a portion indicated as A in FIG. 3. In the figure, it is shown that, as described above, the first layer or thin polysilicon layer 4a of 300 to 500 angstroms makes the grain of polysilicon layer small. The oxide layer 4b as second layer prevents the grain growth of the first layer made of polysilicon.
As described above, the triple layered floating gate has a very thin first layer adjacent to the tunneling oxide layer, which first layer is made of polysilicon of small grains, thereby to mitigate the roughness of the interface between the tunneling oxide layer 3 and the floating gate 4.
However, the above described technique has a severe problem that if the layer 4b as the second layer is too thin, the polysilicon grains become large, and if the layer 4b is too thick, the layer acts as an interposed insulating layer between the first layer and the third layer and as a result, the floating gate does not exhibit the inherent functioning as the floating gate.